1. Technical Field
The present invention relates to a multi-chip package, and, to a multi-chip package which adopts an electrowetting liquid lens for allowing chip selection to be easily performed by changing the focus of the lens.
In the semiconductor industry, packaging technologies for integrated circuits have continuously been developed to satisfy the demand toward miniaturization and mounting reliability. For example, the demand toward miniaturization has expedited the development of technologies for a package with a size approaching to that of a chip, and the demand toward mounting reliability has highlighted the importance of packaging technologies for improving the efficiency of mounting work and mechanical and electrical reliability after mounting.
2. Related Art
As miniaturization and high performance are demanded in electric and electronic products, various technologies for providing a semiconductor package of high capacity have been researched and developed. A method for providing a semiconductor package of high capacity includes the high integration of a memory chip. Such high integration can be realized by integrating an increased number of cells in a limited space of a semiconductor chip.
However, the high integration of a memory chip requires technologies having a high amount precision. These high precision technologies may include the implementation of a fine line width, and a lengthy development period. Under these situations, a stacking technology has been suggested as another method for providing a semiconductor package of high capacity.
The stacking technology is divided into a method of embedding two stacked chips into one package and a method of stacking two separate packages which are independently packaged. Nevertheless, the method of stacking two separate packages has limitations in terms of the height of a resultant semiconductor package when considering the trend toward miniaturization of electric and electronic products.
Therefore, research for a stack package or a multi-chip package in which two or three chips are embedded in one package has been actively conducted.
Meanwhile, a stacked package requires a technology for selecting any one semiconductor chip to be driven among a plurality of semiconductor chips.
For example, the following methods may be used in order to select any one semiconductor chip from in a stacked package; a method for manufacturing semiconductor chips included in each semiconductor package to have different structures, a method for forming different redistribution lines on semiconductor chips with the same structure, or a method of arranging semiconductor chips in a step-like shape and disposing conductive wires on the respective chips to have different arrangements.
However, a method for electrically connecting a substrate and respective semiconductor chips using wires has been generally known in the art. This method has various problems as described below.
First, since wire bonding processes should be performed when stacking each semiconductor chip, a UPH (unit per hour) is reduced, and the number of wires and the number of bonding processes performed therefor serve as a factor that increases the manufacturing cost.
Second, as the thickness of a semiconductor chip gradually decreases, a fail such as bouncing or a crack due to warpage of the semiconductor chip is likely to occur when performing the wire bonding process, and when performing a molding process, wires are likely to be short-circuited due to a wire sweeping phenomenon.
Third, in a structure in which long wires are needed depending upon the number of semiconductor chips to be stacked and a flip chip package is adopted, difficulties exist in transferring electrical signals, and thus, limitations are caused in realizing a high density stack type semiconductor package.
According to these facts, recently, in order to overcome the problems caused in a stack package using metal wires, preventing the electrical characteristics of the stack package from deteriorating and enable miniaturization, research for a stack package using through-silicon vias (TSVs) has been actively conducted.
When stacking individual semiconductor chips in a stack package using TSVs, adhesives are interposed between the TSVs of the semiconductor chips which are brought into contact with each other, and a liquid phase filler is filled in the space between the semiconductor chips excluding the adhesives through an underfill process, by which the respective semiconductor chips are electrically and physically connected with each other.
However, even in the conventional stack packages using through-silicon vias, in order to select a specified semiconductor chip among a plurality of semiconductor chips, via patterns for chip selection should be formed in conjunction with the number of semiconductor chips to be stacked. If a plurality of via patterns is required for chip selection, difficulties are likely to be caused in terms of process and design.